1. Field of the Invention
The present invention relates to a frame synchronization apparatus and its control method. More particularly, the present invention relates to a frame synchronization apparatus capable of establishing a frame synchronization in a stable manner and in a short period of time and relates to a control method of the apparatus.
2. Description of the Related Art
In recent years, the hand phone technology and the radio digital transmission technology have been growing impressively. The radio digital transmission technology includes the digital broadcasting technologies such as the satellite and ground broadcasting technologies as well as the radio LAN (Local Area Network) technology. In comparison with the wire system, the radio digital transmission system is easily affected by the external environment such as the shape of the transmission route, buildings and the weather. It is thus necessary to establish a radio synchronization in a stable manner in an even worse transmission environment.
The radio synchronization cited above means a synchronization with a symbol timing, a synchronization with a frame timing and a synchronization with the frequency of a carrier. In synchronizations including and following a frame-timing synchronization, in general, a synchronization technology making use of a known signal inserted periodically into a transmitted signal is adopted widely.
In a poor transmission environment, by raising the power to transmit the known signal or lengthening the time to transmit the signal, the synchronization performance can be improved. If the transmission power of the known signal is raised or the transmission time of the known signal is lengthened, however, the power to transmit a data signal or the time to transmit the data signal decreases relatively in comparison with those of the known signal. Thus, the efficiency of the data transmission deteriorates.
As a requirement raised by the background described above, there is a strong demand for implementation of synchronization technologies each capable of establishing a state of synchronization without much degrading the efficiency of the data transmission. Such synchronization technologies are disclosed in documents such as Japanese Patent Laid-open No. Hei 10-155004 (hereinafter referred to as Patent Document 1), Japanese Patent Laid-open No. Hei 10-190762 (hereinafter referred to as Patent Document 2), Japanese Patent Laid-open No. Hei 8-307408 (hereinafter referred to as Patent Document 3), Japanese Patent Laid-open No. Hei 6-252966 (hereinafter referred to as Patent Document 4). The synchronization technologies disclosed in the patent references can each be essentially represented by a frame synchronization circuit shown in FIG. 1. FIG. 1 is a block diagram showing the configuration of the existing frame synchronization circuit.
The existing frame synchronization circuit 1 shown in FIG. 1 includes a delay wave detector 11, a correlator 12, a power-value computation circuit 13, a peak detector 14, a deviation-angle computation circuit 15 and a storage circuit 16.
The delay wave detector 11 includes a processor 21 and a delay circuit 22. The processor 21 is a section for carrying out a complex multiplication process to multiply each current symbol in a received delay wave detection series by the complex conjugate of a symbol delayed by the delay circuit 22 from the current symbol by 1 symbol and supplying a product obtained as a result of the complex multiplication process to the correlator 12. The received delay wave detection series is a complex-symbol array of an input signal which is a digital modulated signal supplied by an external source to the delay wave detector 11 by way of an element such as an antenna or a RF (Radio Frequency) circuit. Provided at a stage preceding the delay wave detector 11, the antenna or the RF (Radio Frequency) circuit itself is not shown in the figure. In the following description, the product obtained as a result of the complex multiplication process is referred to as a received delay wave detection value.
The correlator 12 is a section for identifying a correlation between a received delay wave detection series and a known delay wave detection series and supplying a correlation value representing the identified correlation to the power-value computation circuit 13 and the deviation-angle computation circuit 15. The received delay wave detection series is a symbol array of the delay wave detection values received from the delay wave detector 11. The known delay wave detection series is defined as a symbol array of correct delay wave detection values of a known input series which is a symbol array of known values periodically inserted into the received signal. In the following description, the correct delay wave detection values of a known input series are also each referred to as a known delay wave detection value. The power-value computation circuit 13 provided at a stage following the correlator 12 is a section for computing a sum of the square of the I component of the correlation value and the square of the Q component of the correlation value to find an electric power to be supplied to the peak detector 14 provided at a stage following the power-value computation circuit 13. The peak detector 14 is a section for detecting a peak timing appearing in frame synchronization as the timing of the peak of the power and outputting a frame synchronization pulse in 1 symbol time segment with the peak timing.
A process carried out by the peak detector 14 to detect the peak timing is explained by referring to FIG. 2 as follows. In FIG. 2, the vertical axis represents the power value whereas the horizontal axis represents the time. The larger the vertical-axis coordinate, the larger the power value. Time lapses in the right direction along the horizontal axis.
In the waveform shown in FIG. 2, a signal power S in a peak detection process is the power of a signal appearing with a peak timing whereas a noise power N in the peak detection process represents the variance of power variations occurring at times other than a time corresponding to the peak timing. The peak detector 14 detects the first peak timing and outputs a frame synchronization pulse in 1 symbol time segment with the peak timing. Thereafter, the peak detector 14 detects the second peak timing after 1 frame period following the first peak timing, the third peak timing after 1 frame period following the second peak timing and so on. That is to say, the peak detector 14 detects a peak timing for every frame period and outputs a frame synchronization pulse in 1 symbol time segment with the peak timing.
The reader is requested to refer back to FIG. 1. The deviation-angle computation circuit 15 is a section for finding a deviation angle which is defined as arctan (Q/I) where notations Q and I denote respectively the Q and I components of the correlation value output by the correlator 12. The deviation-angle computation circuit 15 supplies the deviation angle to the storage circuit 16. The deviation angle computed with the timing of the frame synchronization pulse is held in the storage circuit 16, which is a section for finding a difference between the frequency of the carrier and the local-oscillation frequency of the receiver apparatus as the output of the storage circuit 16. The difference between the frequency of the carrier and the local-oscillation frequency of the receiver apparatus is used for the purpose of eliminating a frequency error included in the received signal as follows: A reversed rotation with a phase rotation magnitude corresponding to the frequency difference is added to the received signal. It is to be noted, however, that this feature is not shown in the figure.
As described above, the existing frame synchronization circuit 1 shown in FIG. 1 carries out a delay wave detection process before determining a correlation. Thus, a fixed correlation output can be obtained even if a frequency error exists in the received signal to a certain degree. As a result, the frame synchronization circuit 1 is characterized in that a frame synchronization can be established in a stable manner. That is to say, since a phase rotation caused by the frequency error can be stopped by carrying out the delay wave detection process, same-direction phases are cumulatively added to each other in the correlation detection process so that a large correlation output can be obtained.
Next, the delay wave detection process is explained quantitatively by making use of a concrete mathematical expression.
A delay wave detection output is expressed by Eq. (1) given below. In the equation, notation rn denotes a received delay wave detection series, notation Δf denotes the frequency error, notation T denotes the symbol period and notation θ0 denotes a phase shift generated in the transmission line and an analog circuit included in the transmitter apparatus.
                                                                                          r                  n                                ⁢                                  r                                      n                    -                    1                                    *                                            =                            ⁢                                                a                  n                                ⁢                                                      ⅇ                                          j                      ⁡                                              (                                                                              2                            ⁢                                                                                                                  ⁢                                                          πΔ                              ⁢                              ft                                                                                +                                                      θ                            0                                                                          )                                                                              ·                                      a                                          n                      -                      1                                        *                                                  ⁢                                  ⅇ                                      -                                          j                      ⁡                                              (                                                                              2                            ⁢                            πΔ                            ⁢                                                                                                                  ⁢                                                          f                              ⁡                                                              (                                                                  t                                  -                                  T                                                                )                                                                                                              +                                                      θ                            0                                                                          )                                                                                                                                                                    =                            ⁢                                                                    a                    n                                    ⁢                                      a                                          n                      -                      1                                        *                                    ⁢                                      ⅇ                                          j2πΔ                      ⁢                                                                                          ⁢                      fT                                                                      =                                                      a                    n                                    ⁢                                      a                                          n                      -                      1                                        *                                    ⁢                                      ⅇ                    jΔθ                                                                                                          (        1        )            
It is to be noted that, in Eq. (1), an equation of Δθ=2πΔfT holds true. This expression represents a frequency error per symbol. In addition, if the BPSK (Binary Phase Shift Keying) technique is adopted as the modulation method and if the amplitude of the received signal is assumed to have been normalized to 1, an equation of an=ejkπ (where k=0 or 1) holds true. Since ana*n-1 is also represented by an expression of ejk′π (where k′=0 or 1), the delay wave detection output can be expressed by a diagram of FIG. 3.
FIG. 3 is a diagram showing a mapping pattern on a complex plane of the delay wave detection output generated by the delay wave detector 11. In the following description, the complex plane is also referred to as an IQ plane. The I axis represents the I component representing the real part of a correlation value whereas the Q axis represents the Q component of the imaginary part of the correlation value. In the following description, the I and the Q axes are also referred to as the in-phase axis and the orthogonal axis respectively. On the IQ plane shown in FIG. 3, notation Δθ denotes a phase rotation angle generated due to the frequency error as a phase rotation angle per symbol.
That is to say, the received delay wave detection value has a phase rotated by +Δθ from the known delay wave detection value. The received delay wave detection value is a delay wave detection value between adjacent symbols in a received delay wave detection series, being a value delayed from the corresponding known delay wave detection value in the known delay wave detection series. The known delay wave detection value is a delay wave detection value in the known delay wave detection series.
In addition, in a known-signal time segment, the pattern of k′ after the delay wave detection process is also known. Thus, by taking the pattern as the known delay wave detection series and identifying the correlation with the received delay wave detection series of the delay wave detection outputs, a correlation value of KejΔσ at the peak timing can be obtained as shown in FIG. 4. Much like FIG. 3, FIG. 4 also shows the IQ plane. Notation K denotes a number obtained as a result of subtracting 1 from a known-symbol count inserted into the head of every frame of the input signal. The value of K is equal to the number of cumulative addition circuits used in the correlation processing. That is to say, the phase of the known delay wave detection value of the known delay wave detection series and the phase of the received delay wave detection value of the received delay wave detection series corresponding to the known delay wave detection series approach the same value as the value of Δθ decreases in such a way that, the smaller the value of Δθ, the better the phases approach the same value. In addition, for small values of Δθ, a positive correlation can also be said to be stronger.
As described above, in the existing frame synchronization circuit 1 shown in FIG. 1, the correlation value has a phase offset depending on the frequency error. By detecting a peak power value, however, the effect of the phase offset can be eliminated so that it is possible to establish a frame synchronization not dependent on the frequency error.
The existing frame synchronization circuit 1 shown in FIG. 1 executes frame synchronization control as explained above.